dr.ir. Bolatkale
Parttime Associate Professor
Electronic Instrumentation (EI), Department of Microelectronics
Electronic Instrumentation (EI), Department of Microelectronics
PhD thesis (Oct 2013): High Speed and Wide Bandwidth Delta-Sigma ADCs
Promotor: Kofi Makinwa, L. Breems
Expertise: High Speed ADCs, Delta-Sigma Modulators, Hybrid ADCs, Mixed-signal System modeling
Themes: Precision AnalogBiography
Muhammed Bolatkale received his B. Sc. (high honors) degree from Middle East Technical University, Turkey, in 2004 and the M. Sc. (cum laude) and Ph.D. degrees in Electrical Engineering from Delft University of Technology, the Netherlands, in 2007 and 2013.
Since 2007, he has worked for NXP Semiconductors, specializing in wideband Delta-Sigma ADCs for wireless communications and automotive applications.
Dr. Bolatkale received the ISSCC 2016 & 2011 Jan Van Vessem Award for Outstanding European Paper and the IEEE Journal of Solid-State Circuits 2016 and 2011 Best Paper Award.
Publications
- A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme
Javvaji, Sundeep; Bolatkale, Muhammed; Bajoria, Shagun; Rutten, Robert; Essink, Bert Oude; Beijens, Koen; Makinwa, Kofi A. A.; Breems, Lucien J.;
IEEE Journal of Solid-State Circuits,
Volume 59, Issue 4, pp. 1184-1193, 2024. DOI: 10.1109/JSSC.2024.3354574
Keywords: ...
Quantization (signal);1/f noise;Resistors;Capacitors;Inverters;Clocks;Switches;Analog-to-digital converter (ADC);continuous time (CT);delta–sigma (ΔΣ);multi-path chopping;wideband receiver. - A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme
Javvaji, Sundeep; Bolatkale, Muhammed; Bajoria, Shagun; Rutten, Robert; Essink, Bert Oude; Beijens, Koen; Makinwa, Kofi A. A.; Breems, Lucien J.;
IEEE Journal of Solid-State Circuits,
Volume 59, Issue 4, pp. 1184-1193, 2024. DOI: 10.1109/JSSC.2024.3354574
Keywords: ...
Quantization (signal);1/f noise;Resistors;Capacitors;Inverters;Clocks;Switches;Analog-to-digital converter (ADC);continuous time (CT);delta–sigma (ΔΣ);multi-path chopping;wideband receiver. - A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW
Javvaji, Sundeep; Bolatkale, Muhammed; Bajoria, Shagun; Rutten, Robert; Essink, Bert Oude; Beijens, Koen; Makinwa, Kofi; Breems, Lucien;
In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits),
pp. 1-2, 2023. DOI: 10.23919/VLSITechnologyandCir57934.2023.10185356 - A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC
Mehrotra, Shubham; Eland, Efraïm; Karmakar, Shoubhik; Liu, Angqi; Gönen, Burak; Bolatkale, Muhammed; Van Veldhoven, Robert; Makinwa, Kofi A.A.;
In ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC),
pp. 253-256, 2022. DOI: 10.1109/ESSCIRC55480.2022.9911295 - A 3.2mW SAR-assisted CTSD ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS
P. Cenci; M. Bolatkale; R. Rutten; M. Ganzerli; G. Lassche; K. Makinwa; L. Breems;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
6 2019. DOI: 10.23919/VLSIC.2019.8778176 - A 3.2mW SAR-assisted CTSD ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS
P. Cenci; M. Bolatkale; R. Rutten; M. Ganzerli; G. Lassche; K. Makinwa; L. Breems;
In Dig. Techn. Paper IEEE Symposium on VLSI Circuits (VLSI),
pp. C230-C231, 6 2019. DOI: 10.23919/VLSIC.2019.8778176 - A 28 nm 2 GS/s 5-b Low-latency SAR ADC with gm-boosted StrongARM Comparator
P. Cenci; M. Bolatkale; R. Rutten; G. Lassche; K. Makinwa; L. Breems;
In European Solid-State Circuits Conference (ESSCIRC),
2017. DOI: 10.1109/ESSCIRC.2017.8094553 - A 28 nm 2 GS/s 5-b Low-latency SAR ADC with gm-boosted StrongARM Comparator
P. Cenci; M. Bolatkale; R. Rutten; G. Lassche; K. Makinwa; L. Breems;
In European Solid-State Circuits Conference (ESSCIRC),
pp. 171-174, 2017. DOI: 10.1109/ESSCIRC.2017.8094553 - A 4 GHz continuous-time ΔΣ ADC with 70 dB DR and -74 dBFS THD in 125 MHz BW
M. Bolatkale; L.J. Breems; R. Rutten; K.A.A. Makinwa;
IEEE Journal of Solid State Circuits,
Volume 46, Issue 12, pp. 2857-2868, December 2011. - A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33μV/°C Offset Drift
M. Bolatkale; M. A. P. Pertijs; W. J. Kindt; J. H. Huijsing; K. A. A. Makinwa;
IEEE Journal of Solid-State Circuits,
Volume 46, Issue 9, pp. 2099‒2107, September 2011. DOI: 10.1109/JSSC.2011.2139530
Abstract: ...
A MOS-input operational amplifier has a reconfigurable input stage that enables trimming of both offset and offset drift based only on single-temperature measurements. The input stage consists of a MOS differential pair, whose offset drift is predicted from offset voltage measurements made at well-defined bias currents. A theoretical motivation for this approach is presented and validated experimentally by characterizing the offset of pairs of discrete MOS transistors as a function of bias current and temperature. An opamp using the proposed single-temperature trimming technique has been designed and fabricated in a 0.5 μm BiCMOS process. After single-temperature trimming, it achieves a maximum offset of ± 30 μV and an offset drift of 0.33 μV/°C (3σ) over the temperature range of -40°C to +125°C. - A 4GHz CT Delta-Sigma ADC with 70dB DR and -74dBFS THD in 125MHz BW
M. Bolatkale; L.J. Breems; R. Rutten; K.A.A. Makinwa;
In A Chandrakasana; W Gass (Ed.), 2011 IEEE International Solid-State Circuits Conference (ISSCC),
IEEE, pp. 470-472, 2011. - High-speed sigma-delta converters
M. Bolatkale; L.J. Breems; K.A.A. Makinwa;
s.n. (Ed.);
ProRISC, , pp. 143-148, 2008. - A BiCMOS Operational Amplifier Achieving 0.33μV/°C Offset Drift using Room-Temperature Trimming
M. Bolatkale; M. A. P. Pertijs; W. J. Kindt; J. H. Huijsing; K. A. A. Makinwa;
In Dig. Techn. Papers IEEE International Solid-State Circuits Conference (ISSCC),
IEEE, pp. 76‒77, February 2008. DOI: 10.1109/isscc.2008.4523064
BibTeX support
Last updated: 15 Jul 2019
