[2026] High-Voltage Tolerant Low-Power Front-End for Closed-Loop Neural Modulation (project with Newronika) [open]

Closed-loop Deep Brain Stimulation (DBS) represents the next frontier in treating neurological disorders such as Parkinson’s disease and Epilepsy. Unlike traditional "always-on" stimulation, closed-loop systems sense neural biomarkers and deliver electrical pulses only when needed. This approach minimizes side effects and extends the battery life of Implantable Medical Devices (IMDs).

A major bottleneck in these systems is the interface between the high-voltage stimulator and the sensitive recording front-end. To achieve effective stimulation, the stimulator ASIC often requires a high-voltage supply (e.g., 20V) to drive sufficient current through high-impedance electrodes. Conversely, the recording ASIC must be "always-on" to monitor brain activity and is typically powered by a low-voltage supply (e.g., 3.3V) to minimize power consumption.

When stimulation occurs, the electrodes can experience large common-mode (CM) voltage swings that exceed the supply rails of the recording ASIC. To save power, the high-voltage supply is only active during the low duty-cycle stimulation phase. Therefore, the recording front-end cannot simply be powered by the high-voltage rail. The challenge lies in designing a recording architecture that remains functional and safe while the input common-mode signal shifts up to 20V, all while operating from a 3.3V rail and detecting micro-volt level neural signals.

Assignment

The goal of this project is to design a low-power, multi-channel neural recording front-end capable of "beyond-the-rails" operation. The circuit must tolerate input common-mode signals significantly higher than its supply voltage without gate oxide breakdown or signal clipping. The work will span literature review to drive an architectural choice, circuit dimensioning, full custom design, and layout, with a tapeout as the end goal. The design will be implemented in 180‑nm BCD CMOS technology. The student will be supported with a salary for up to 12 months and will carry out the project at Newronika’s headquarters in Milan, Italy, under the co‑supervision of an industry expert.

Requirements

MSc EE‑ME student.

You should be comfortable with analog mixed‑signal IC design and the Cadence analog environment. Curiosity, hard work, and creativity are always needed. If you are interested, contact Dr. Dante Muratore via email with a motivation letter and your (tentative) IEP.

Required courses: Analog CMOS 1 and Nyquist-Rate Data Converters

Contact

Last modified: 2026-03-18