MSc ME Thesis Presentation

Off-chip Self Timed SNN Custom Digital Interconnect System

Yichen Yang

To support the spike propagates between neurons, neuromorphic computing systems always require a high-speed communication link.

Meanwhile, spiking neural networks are event-driven so that the communication links normally exclude the clock signal and related blocks.

This thesis aims to develop a self-timed off-chip interconnect system with ring topology that supports multi-point communication in neuromorphic computing systems. This interconnect system is implemented in high-level modeling with SystemC and involves the burstmode two-wire protocol in point-to-point communication. In order to ensure the flexibility of the system, the distributed control system is involved. Further, the system can be configured with different numbers of chiplet to fulfill various spiking neural network structures.

We also explore optimization methods, which is a bi-directional ring topology achieving the growth of throughput. Based on evaluation and simulation results, the interconnect system can achieve 4.57Gbps with the specific application scenario.

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Overview of MSc ME Thesis Presentation