Jing Li presents Ultrasound Receiver with Pitch-Matched ADCs at VLSI

At the 2019 VLSI Circuits Symposium in Kyoto, Japan, Dr. Jing Li of the Ultrasound ASICs group presented an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150μm element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2×2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.

Jing Li spent one year as visiting researcher in Michiel Pertijs' Ultrasound ASICs group at the Electronic Instrumentation Laboratory. He is now with the University of Electronic Science and Technology of China, Chengdu, China.

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